The present invention relates to a to-be-mounted electronic component to which functional alloy plating using a bonding material for mounting is applied with a substitute bonding material for solder (tin-lead alloy), and aims at providing alloy plating which has been put to a practical use in such a way that the function of existing alloy plating of this type has been significantly improved to eliminate toxic plating from various kinds of electronic components for use in electronic devices so that it is useful in protecting the environment.
As solder which does not use lead (Pb) (Pb-free solder), various new bonding agents have been developed and their properties become apparent. And, the stage is proceeding to the development of their manufacturing methods. Tin (Sn)-bismuth (Bi), Sn-indium alloy (In), Sn-zinc alloy (Zn), Sn plating etc. are considered as Pb-free solder to devices. The cost for the Snxe2x80x94In alloy among them is extremely high, about 25 times the cost for Snxe2x80x94Bi. The Snxe2x80x94Zn alloy has a problem on the solderability after heat resistance because Zn is prone to be oxidized. This leaves Snxe2x80x94Ag, Snxe2x80x94Bi and Sn.
Bi on copper may be thermally diffused at the time of reflow and may be peeled, so that Snxe2x80x94Bi for devices should have nickel applied as a base in order to avoid the peeling.
If a coat offset (melt-originated offset) occurs when a surface-mounting device is melted, the bonding surface has a rough surface, so that the bonding surface becomes smaller, thus lowering the bonding strength. Prevention of a melt-originated offset which makes organic eutectoid in a coat extremely small is attempted by applying plating according to this invention.
Conventionally, solder (tin-lead alloy) has been used for a long time as a bonding material for mounting electronic device components. Recently, the harmfulness of lead has been noticed mainly in America and Europe and removal of lead from electronic devices has progressed rapidly.
Meanwhile, in Japan has already started a movement of voluntary removal mainly by the electronics industry.
Electroplating is applied to most of materials for to-be-mounted electronic components as tinning. Therefore, there is a pressing need to industrialize plating of substitute alloys for the industrial growth.
As solder which is an essential bonding material for the aforementioned electronic components contain lead (Pb), however, when electronic devices are disposed of, lead would be melted and seep into groundwater from a junk yard, raising a problem of environmental pollution, unless electronic components having to-be-mounted parts containing solder""s lead are removed.
Accordingly, it is an object of this invention to overcome the problem of the prior art and to provide electronic components to be on which very practical alloy plating for bonding that is the existing alloy plating of this type which has been improved significantly is applied using a substitute metal for lead in solder alloy plating.
The first of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that with Sn as a base, one of Bi, Ag and Cu is selected, a Bi content to the Sn is set to 1.0% or less, the Bi content to the Sn is set to 2.0 to 10.0%, an Ag content to the Sn is set to 1.0 to 3.0%, the Ag content to the Sn is set to 3.0 to 5.0%, the Ag content to the Sn is set to 8.0 to 10.0%, or a Cu content to the Sn is set to 0.5 to 1.0%, and an electrolytic process is performed with a special waveform.
The second of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an IC chip is wire-bonded to a lead frame and outer leads exposed outside a molded IC package are subjected to an electrolytic process with a Bi content to Sn whose content is 99.0% or greater being set to 1.0% or less and with a special waveform.
The third of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an IC chip is wire-bonded to a lead frame and outer leads exposed outside a molded IC package are subjected to an electrolytic process with a Bi content to Sn whose content is 98.0 to 90.0% being set to 2.0 to 10.0% and with a special waveform.
The fourth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an IC chip is wire-bonded to a lead frame and outer leads exposed outside a molded IC package are subjected to an electrolytic process with an Ag content to Sn whose content is 99.0 to 97.0% being set to 1.0 to 3.0% and with a special waveform.
The fifth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an IC chip is wire-bonded to a lead frame and outer leads exposed outside a molded IC package are subjected to an electrolytic process with an Ag content to Sn whose content is 97.0 to 95.0% being set to 3.0 to 5.0% and with a special waveform.
The sixth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an IC chip is wire-bonded to a lead frame and outer leads exposed outside a molded IC package are subjected to an electrolytic process with an Ag content to Sn whose content is 92.0 to 90.0% being set to 8.0 to 10.0% and with a special waveform.
The seventh of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an IC chip is wire-bonded to a lead frame and outer leads exposed outside a molded IC package are subjected to an electrolytic process with a Cu content to Sn whose content is 99.5 to 99.0% being set to 0.5 to 1.0% and with a special waveform.
The eighth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an electrode pattern of a printed circuit board is subjected to an electrolytic process with a Bi content to Sn whose content is 99.0% or greater being set to 1.0% or less and with a special waveform.
The ninth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an electrode pattern of a printed circuit board is subjected to an electrolytic process with a Bi content to Sn whose content is 98.0 to 90.0% being set to 2.0 to 10.0% and with a special waveform.
The tenth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an electrode pattern of a printed circuit board is subjected to an electrolytic process with an Ag content to Sn whose content is 99.0 to 97.0% being set to 1.0 to 3.0% and with a special waveform.
The eleventh of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an electrode pattern of a printed circuit board is subjected to an electrolytic process with an Ag content to a content of 97.0 to 95.0% being set to 3.0 to 5.0% and with a special waveform.
The twelfth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an electrode pattern of a printed circuit board is subjected to an electrolytic process with an Ag content to a content of 92.0 to 90.0% being set to 8.0 to 10.0% and with a special waveform.
The thirteenth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that an electrode pattern of a printed circuit board is subjected to an electrolytic process with a Cu content to Sn whose content is 99.5 to 99.0% being set to 0.5 to 1.0% and with a special waveform.
The fourteenth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that a chip tantalum capacitor is wire-bonded to a lead frame and outer leads exposed outside the chip tantalum capacitor are subjected to an electrolytic process with a Bi content to Sn whose content is 99.0% or greater being set to 1.0% or less and with a special waveform.
The fifteenth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that a chip tantalum capacitor is wire-bonded to a lead frame and outer leads exposed outside the chip tantalum capacitor are subjected to an electrolytic process with a Bi content to Sn whose content is 98.0 to 90.0% being set to 2.0 to 10.0% and with a special waveform.
The sixteenth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that a chip tantalum capacitor is wire-bonded to a lead frame and outer leads exposed outside the chip tantalum capacitor are subjected to an electrolytic process with an Ag content to Sn whose content is 99.0 to 97.0% being set to 1.0 to 3.0% and with a special waveform.
The seventeenth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that a chip tantalum capacitor is wire-bonded to a lead frame and outer leads exposed outside the chip tantalum capacitor are subjected to an electrolytic process with an Ag content to Sn whose content is 97.0 to 95.0% being set to 3.0 to 5.0% and with a special waveform.
The eighteenth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that a chip tantalum capacitor is wire-bonded to a lead frame and outer leads exposed outside the chip tantalum capacitor are subjected to an electrolytic process with an Ag content to Sn whose content is 92.0 to 90.0% being set to 8.0 to 10.0% and with a special waveform.
The nineteenth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that a chip tantalum capacitor is wire-bonded to a lead frame and outer leads exposed outside the chip tantalum capacitor are subjected to an electrolytic process with a Cu content to Sn whose content is 99.5 to 99.0% being set to 0.5 to 1.0% and with a special waveform.
The twentieth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that general electronic device component materials including a component material which needs plating for bonding and a general component material which needs plating as a functional component are subjected to an electrolytic process with a Bi content to Sn whose content is 99.0% or greater being set to 1.0% or less and with a special waveform.
The twenty-first of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that general electronic device component materials including a component material which needs plating for bonding and a general component material which needs plating as a functional component are subjected to an electrolytic process with a Bi content to Sn whose content is 98.0 to 90.0% being set to 2.0 to 10.0% and with a special waveform.
The twenty-second of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that general electronic device component materials including a component material which needs plating for bonding and a general component material which needs plating as a functional component are subjected to an electrolytic process with an Ag content to Sn whose content is 99.0 to 97.0% being set to 1.0 to 3.0% and with a special waveform.
The twenty-third of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that general electronic device component materials including a component material which needs plating for bonding and a general component material which needs plating as a functional component are subjected to an electrolytic process with an Ag content to Sn whose content is 97.0 to 95.0% being set to 3.0 to 5.0% and with a special waveform.
The twenty-fourth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that general electronic device component materials including a component material which needs plating for bonding and a general component material which needs plating as a functional component are subjected to an electrolytic process with an Ag content to Sn whose content is 92.0 to 90.0% being set to 8.0 to 10.0% and with a special waveform.
The twenty-fifth of this invention is functional alloy plating using substitute bonding material for Pb and electronic component to be mounted to which the functional alloy plating is applied, characterized in that general electronic device component materials including a component material which needs plating for bonding and a general component material which needs plating as a functional component are subjected to an electrolytic process with a Cu content to Sn whose content is 99.5 to 99.0% being set to 0.5 to 1.0% and with a special waveform.
[EMBODIMENT]
[Significance of Special Waveform]
A description will now be given of the aforementioned xe2x80x9celectrolytic process with a special waveformxe2x80x9d. First, typical electroplating is DC plating, i.e., plating with a voltage having an AC voltage rectified by a rectifier.
To perform plating, it is necessary to combine and add several types of organic additives into a plating solution so that the crystal grain size of metal to be deposited does not become resin particle size.
Of course, those organic materials become eutectoid at the same time as the metal to be plated, causing many defects on their functions as bonding materials.
The xe2x80x9celectrolytic process with a special waveformxe2x80x9d in this invention improves those shortcomings, and an additive to be added into a plating solution is only a slight amount of a surface active agent which is not decomposed and disposed, and this special waveform serves as an organic additive.
In this invention, the special waveform is a pulse waveform which is acquired for an electrolytic process from a current that has been rectified with a thyristor 6-phase half wave. Thus, the electrolytic process uses a pulse waveform which can cycle between positive and negative.
The following shows a table of the types of mass-producible platings.
As there are different coat characteristics to be acquired depending on whether the lead types of devices to be used are lead lines, a lead frame or leadless, they should be selectively used, but the added values of the devices differ device by device so that a cost-based selection is also considered as an important factor.
In the comparison of the costs for plating materials, the cost for the base acid is high even if an inexpensive metal is used, so that the cost does not decrease as indicated in the comparison of the prices of metals. A further variation is seen when it is run as plating.
Then, the following table shows the evaluation of Pb-free coats as coats.
The following table shows a list of the evaluation of the individual coats.
The following table shows the costs for the individual coats.
While the samples shown above had a nickel (Ni) base to avoid diffusion on copper, Snxe2x80x94Ag showed such a phenomenon that oxidization on Ni through Ag at the time of heat resistance lowered the bondability. In this respect, it is contemplated that copper (Cu) is suitable as the base for Snxe2x80x94Ag. Further, heat-resistance-originated discoloration and melt-originated offset also occurred. To cope with this melt-originated offset, it is necessary to obtain Snxe2x80x94Ag plating containing 85% or more of Ag, which is naturally a factor to increase the cost. Slight segregation is seen on the surface of Snxe2x80x94Bi. Snxe2x80x94Ag and Sn-special waveform plating still suffer poor solution efficiencies and the line speeds remain about a half the speed of the current special-waveform plating. Although solution conditions were so set as to provide the optimal appearance in the implementation of the scheme, improvements can be made on the density of the solution, the density of the additive, stirring and so forth. In the case of surface mounting, there may be a question on the behavior of Bi, such as segregation or diffusion. In this respect, Bi in the Sn-special waveform plating has a minute amount and serves to adjust the deposition of the plated coat so that it does not seem to raise a problem on segregation or diffusion.
The following gives the results of the evaluation of samples of Snxe2x80x94Ag, Snxe2x80x94Bi and Sn plating to chip tantalum frames.
(1) Plating Specifications
(2) Test Results
xe2x80x9cSnxe2x80x94Agxe2x80x9d
a. Appearance: passed (free of spot, stain and discoloration)
b. Heat resistance: discoloration present (160xc2x0 C.xc3x976 Hr heat resistance. no expansion, peeling, discoloration and fall-off)
c. Solderability test: passed (after heat resistance, 230xc2x0 C.xc3x973 secxc3x97once n=1)
d. Bending test: passed (after heat resistance, 180xc2x0 C., bend-back test, measured at A n=1)
e. Melt-originated offset: no melt-originated offset (no heat resistance 270xc2x0 C.xc3x9730 minxc3x97once n=1)
f. Peeling test: passed (sample before and after heat resistance n=1)
g. Melting point: 222xc2x0 C.
h. Hardness (Vickers hardness): 16.3
i. Solder wettability: zero-cross time before heat resistance average 0.65 (sec) after heat resistance average 0.95 (sec)
: wet strength before heat resistance average 71.40 (mg) after heat resistance average 26.40 (mg) (n=5)
j. Bonding: before heat resistance average 0.37 (kg) strength: after heat resistance average 0.05 (kg) (n=5)
k. Plating thickness: average 4.03 (xcexcm) (measured with fluorescent X rays n=9)
l. Composition: Sn 92.46%
: Ag 7.54%
xe2x80x9cSnxe2x80x94Bixe2x80x9d
a. Appearance: passed (free of spot, stain and discoloration)
b. Heat resistance: passed (160xc2x0 C.xc3x976 Hr heat resistance. no expansion, peeling, discoloration and fall-off)
c. Solderability test: passed (after heat resistance, 230xc2x0 C.xc3x973 secxc3x97once n=1)
d. Bending test: passed (after heat resistance, 180xc2x0 C., bend-back test, measured at A n=1)
e. Melt-originated offset: no melt-originated offset (no heat resistance 270xc2x0 C.xc3x9730 minxc3x97once n=1)
f. Peeling test: passed (sample before and after heat resistance n=1)
g. Melting point: 228xc2x0 C.
h. Hardness (Vickers hardness): 23.0
i. Solder wettability: zero-cross time before heat resistance average 0.85 (sec) after heat resistance average 0.87 (sec)
: wet strength before heat resistance average 23.0 (mg) after heat resistance average 23.0 (mg) (n=5)
j. Bonding : before heat resistance average 1.56 (kg)
xe2x80x83strength: after heat resistance average 0.56 (kg) (n=5)
k. Plating thickness: average 4.21 (xcexcm) (measured with fluorescent X rays n=9)
l. Composition: Sn 97.31%
: Bi 2.69% (measured at A)
xe2x80x83xe2x80x9cSnxe2x80x9d
a. Appearance: passed (free of spot, stain and discoloration)
b. Heat resistance: discoloration present (160xc2x0 C.xc3x976 Hr heat resistance. no expansion, peeling, discoloration and fall-off)
c. Solderability test: passed (after heat resistance, 230xc2x0 C.xc3x973 secxc3x97once n=1)
d. Bending test: (after heat resistance, 180xc2x0 C., bend-back test, measured at A n=1)
e. Melt-originated offset: no melt-originated offset (no heat resistance 270xc2x0 C.xc3x9730 minxc3x97once n=1)
f. Peeling test: passed (sample before and after heat resistance n=1)
g. Melting point: 232xc2x0 C.
h. Hardness (Vickers hardness): 11.40xc2x0 C.
i. Solder wettabilty: zero-cross time before heat resistance wettability average 0.50 (sec) after heat resistance average 0.61 (sec)
: wet strength before heat resistance average 31.40 (mg) after heat resistance average 34.20 (mg) (n=5)
j. Bonding: before heat resistance average 1.63 (kg)
xe2x80x83strength: after heat resistance average 0.70 (kg) (n=5)
k. Plating thickness: average 3.99 (xcexcm) (measured with fluorescent X rays n=9)
l. Composition: Sn 99.84%
: Bi 0.16% (measured at A)
(3) Evaluation Method and Data
{circle around (1)} Hardness (Vickers hardness) measuring conditions
Measure portion xe2x80x9cAxe2x80x9d of non-heat-resisted samples under the following conditions by using a super light load minute hardness meter (model mvk-1).
a. load: 0.5 fg
b. load keeping time: 15 sec
c. load speed: 0.01 mm/sec
Measure the diagonal line of a dent three times and compute the Vickers hardness from the average dent area.
{circle around (2)} Zero-crossing time, wet strength measuring conditions
Five portions xe2x80x9cAxe2x80x9d of samples S of a frame were sampled from one piece shown in FIG. 1 and were measured under the following conditions using a solder checker (SAT-2000).
a. Sn 60%, Pb 40%
b. TEMP 230xc2x0 C., SPEED 25 mm/sec
c. DEPTH 2 m, SENS 1
d. Flux present (MI L type R used)
(4) Solder Wettability Data
{circle around (1)} The solder wettability data of Snxe2x80x94Ag is illustrated in Table 5.
{circle around (2)} The solder wettability data of Snxe2x80x94Bi is illustrated in Table 6.
{circle around (3)} The solder wettability data of Sn is illustrated in Table 7.
(5) Bonding Strength Measuring Conditions
Cut portion xe2x80x9cCxe2x80x9d under leads at 3 mm in width, and sample ten from two pieces. Place cut samples one on another with a clearance of 0.3 mm and solder-dip under the following conditions using a solder checker.
a. Sn 60%, Pb 40%
b. TEMP 230xc2x0 C., SPEED 25 mm/sec
c. DEPTH 2 mm, SENS 1
d. Flux present (MI L type R used)
Measure the force to peeling by using a push-pull gauge.
(6) Plating Thickness Measuring Portion
Three portions xe2x80x9cAxe2x80x9d, xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d of a sample S of a frame per piece were measured and as there were five pieces of frames, a total of nine portions, both ends and the center, were measured using fluorescent X rays.
(7) Measuring Portions
As shown in FIG. 1, the measuring portions xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d of the sample S of the frame may indicate other portions of the same shapes in one piece. That is, it means that they include the measuring portion xe2x80x9cAxe2x80x9d and portions xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d or the like.
With regard to the evaluation coats, evaluation method and measuring method, the results of the comparison of the characteristics of the individual Pb-free coats as shown in Tables 14 to 16 were obtained.
Examples of this invention will now be described with reference to the accompanying drawings. In the diagrams, xe2x80x9c1xe2x80x9d is a lead frame where a mount component, such as an IC chip, is mounted, and which has an island portion 2 in the center portion and a plurality of outer leads at the periphery.
xe2x80x9c3xe2x80x9d denotes outer leads which become to-be-plated portions and protrude outward of the IC package, and xe2x80x9c4xe2x80x9d is a ball lead portion which becomes a to-be-plated portion as external leads of CSP.
While alloy plating to be applied to the aforementioned to-be-plated portions contains Sn and a plating material other than lead, and the composition is as follows. The set ratios are Bi=1.0% with respect to Sn=99.0% in the first example, and Bi=2.0 to 10.0% with respect to Sn=98.0 to 90.0% in the second example. The ratio is set to Ag=1.0 to 3.0% with respect to Sn=99.0 to 97.0% in the third example. The ratio is set to Ag=3.0 to 5.0% with respect to Sn=97.0 to 95.0% in the fourth example. The ratio is set to Ag=8.0 to 10.0% with respect to Sn=92.0 to 90.0% in the fifth example. The ratio is set to Cu=0.5 to 1.0% with respect to Sn=99.5 to 90.0% in the sixth example.
xe2x80x9c5xe2x80x9d is an IC chip, a mount component, to be mounted on the lead frame 1, xe2x80x9c5xe2x80x2xe2x80x9d is an LSI chip, and xe2x80x9c5xe2x80x3xe2x80x9d is a chip tantalum capacitor. xe2x80x9c6xe2x80x9d denotes inner leads, and xe2x80x9c7xe2x80x9d is a package which has the IC chip 5 or the LSI chip 5xe2x80x2 molded with a resin. FIG. 8 shows an IC wafer.
In FIG. 6, xe2x80x9c8xe2x80x9d is an IC wafer in a pretreatment in the IC fabrication process, and a plurality of patterns are formed on the IC wafer of 150 to 200 mm in diameter.
(1) IC Fabrication Process
a. IC wafer step=form a plurality of patterns on the IC wafer (FIG. 6) of 150 to 200 mm in diameter. There are actually over 300 steps to this step.
b. Dicing=dice the IC wafer 8 into individual semiconductor IC chips 5 (FIG. 6). The above are pretreatments.
c. Die bonding=adhere and fix the IC chip 5 to the island portion 1xe2x80x2 of the lead frame 1 (FIG. 7).
d. Wire bonding=bond the IC chip 5 to electrodes 3xe2x80x2 of the lead frame 1 and the inner leads 6 (FIG. 7).
e. Resin mold=perform resin molding to form and protect the package 7 (FIG. 8). The above are post-treatments.
(2) IC Assembling Step
a. IC lead frame forming=form the elongated lead frame 1 by press punching and photoetching a rolled thin metal plate (42 alloy, copper alloy) (chain-line portion in FIG. 6).
b. Inner plating=apply gold plating or silver plating to the IC lead frame (island portion 2 and inner leads 6) before resin molding (FIG. 6).
c. Die bonding and wire bonding=bond the IC chip 5 to the island portion 2 of the lead frame. Then, connect the IC chip 5 to the electrodes 3xe2x80x2 of the lead frame 1 by the inner leads 6 (FIG. 7).
d. Resin molding=Seal and fix the IC chip 5 and the inner leads 6 in the package 7 with plastic, such as epoxy resin or silicon resin (FIG. 8).
e. Baking=perform a high-temperature treatment for stabilization after resin molding.
f. Resin variable removal=remove a thin resin coat sticking out over the lead frame 1 at the time of resin molding. Thereafter, perform honing with water jet, resin or glass beads.
g. Outer plating=Plate the outer leads 3 with a Pb-free material according to this invention containing Sn as an essential component and Bi, Ag or Cu by using an electrolytic process with a special waveform with a melting point in a range of 220 to 250xc2x0 C. That is, as the aforementioned alloy plating material, Bi is set to or less 1.0% with respect to Sn=99.0% in the first example, Bi is set to 2.0 to 10.0% with respect to Sn=98.0 to 90.0% in the second example, Ag is set to 1.0 to 3.0% with respect to Sn=99.0 to 97.0% in the third example, Ag is set to 3.0 to 5.0% with respect to Sn=97.0 to 95.0% in the fourth example, Ag is set to 8.0 to 10.0% with respect to Sn=92.0 to 90.0% in the fifth example, and Cu is set to 0.5 to 1.0% with respect to Sn=99.5 to 90.0% in the sixth example.
h. Cutting=cut away the individual IC packages 7 from the linked frames (chain lines K in FIG. 8, chain lines K in FIG. 5).
i. Bend the outer leads 3 according to the intended mounting (FIG. 2 shows mounting on a printed circuit board).
j. Mount the IC package 7 on an electrode pattern 10 of a printed circuit board 9 and solder bonding portions to the outer leads 3 (FIGS. 2 and 3).
In this case, it is placed on the electrode pattern 10 of the printed circuit board 9 that faces the ball leads 4 of BGA or CSP (FIG. 4).
With the above-described structure, this invention eliminates Pb from a solder material as a bonding material which is essential for electronic components in the production of electronic devices, thereby preventing a possible pollution problem such that when electronic devices which become unnecessary are disposed of, Pb leaks and seeps into groundwater.
In mounting electronic components, alloy plating equivalent to or greater than Pb can be acquired without using Pb but by using other bonding materials than Pb.